An Empirical Research on Conductance Effect on on-Chip High Speed VlSI RLCG Interconnection and Transient Analysis Based Delay Model

Abstract

Any system's transient response is determined by its baseline conditions. This paper presents a review of the transient response under diverse settings. Apart from the transient response, this paper aims to provide a review of the influence of conductance on latency under different interconnect methods. Any high-density chip's backbone is its interconnects. Along with the transient response and conductance impact, this paper examines the introduction of high frequency effects such as proximity, skin effect, and electron migration. An RLCG interconnect model is the model being reviewed.