PSO-PID Controller for Interleaved Boost Converter

Abstract

Single-stage topologies use a tiny low-energy storage capacitance resulting in giant low-frequency ripples within the output voltage, but a large-value capacitor will not be able to remove these ripples, the dc-bus capacitance voltage becomes uncontrolled floating. The capacitance voltage at light-load conditions will reach terribly high levels. This imposes a high-voltage stress on the device switches. Several tries are created to cut back this voltage stress by victimization output or dc-bus voltage feedback. However, the most limitation of the single-converter topologies is on the sensible power process capability. This article describes the total harmonic distortion analysis, i.e., to seek out the impact of amendment of input voltage, amendment in load and switch-frequency by implementing a four-parallel boost converter, every parallel converter is of 50 W unit and switched at a 100 kHz. The waveforms area unit discovered victimization MATLAB Simulink.